1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a DLL (delay locked loop) circuit and a method of controlling the same.
2. Related Art
In general, delay locked loops are used to match the phase of a clock input from outside of a semiconductor integrated circuit with the phase of a clock used in the semiconductor integrated circuit.
In a CKE intensive precharge power down mode, when the level of a clock enable signal “CKE” is alternated between a high level and a low level in units of 3 to 4 clocks, precharge power-down does not occur.
FIG. 1 is a block diagram illustrating a conventional delay locked loop according to related art. The delay locked loop shown in FIG. 1 includes a DLL test control unit 30 and a DLL block 20.
The DLL test control unit 30 receives a test mode signal “TM” and outputs a DLL test mode hold control signal “TDLLHOLD.” The DLL test control unit 30 encodes a test mode signal for testing the performance of the DLL block 20.
The DLL block 20 receives an external clock signal “CLK” and generates a DLL clock signal “CLKDLL.” The DLL block 20 includes a DLL clock buffer 21, a clock driver 22, a DLL variable delay unit 23, a DLL delay control unit 26, a replica delay unit 24, a phase detecting unit 25, and a DLL control unit 27.
The operation of the delay locked loop shown in FIG. 1 will now be described in detail. First, when the test mode signal “TM” transitions to a high level, the DLL test mode hold signal “TDLLHOLD” changes to a high level. Therefore, the DLL delay control unit 26 receives a high-level DLL test mode hold signal “TDLLHOLD” and fixes the delay time of the DLL variable delay unit 23. Therefore, the DLL block 20 generates a DLL clock signal “CLKDLL” that has a fixed phase.
However, when entering a CKE intensive precharge power-down mode, in a standby mode of the delay locked loop, a bank is precharged and a clock enable signal “CKE” changes from a high level to a low level. Then, most of the internal circuits are turned off in order to reduce current consumption. The delay locked loop is turned off after a predetermined amount of time has elapsed in the power down mode. At that time, a delay correcting circuit of the delay locked loop is turned on. The delay correcting circuit in the on state updates the phase of the DLL clock.
In a conventional delay locked loop, in a CKE intensive precharge power down mode, for a predetermined period of time after the clock enable signal “CKE” changes from a high level to a low level, a large voltage drop occurs in a DLL voltage (VDDL) that is applied to the delay locked loop, but a small voltage drop occurs in a power supply voltage (VDD) for internal circuits other than the delay locked loop. Therefore, the level of the DLL voltage (VDDL) is lower than that of the power supply voltage (VDD). Accordingly, at the beginning of the power down mode, the phase of the DLL clock is corrected at a high DLL voltage (VDDL), and when the power down mode ends, the phase of the DLL clock is corrected at a low DLL voltage (VDDL). As a result, a phase difference occurs in the DLL clock, and a DLL lock fail occurs in a system supplied with unstable power.